1. Field of the Invention
The present invention relates to a thin film field effect transistor (hereinafter referred to as "thin film FET") and a method of manufacturing the same and, more specifically, to an insulated gate FET having a gate electrode capacity-coupled with a semiconductor channel through an insulating layer or a junction-gate FET having a gate making a rectifying junction with a semiconductor channel layer, and a method of manufacturing such a FET.
2. Description of the Prior Art
The construction of a thin film conventional insulated gate field effect transistor (hereinafter referred to as "insulated gate FET") will be described with reference to FIGS. 36, and 37. In an thin film insulated gate field effect transistor, a source electrode 6 and a drain electrode 7 are joined respectively through second thin semiconductor layers 5a and 5b, namely, doped thin film semiconductor layers, to a first semiconductor layer 4. A gate electrode 2 is capacity-coupled through a gate insulating layer 3 with a channel 8 in the first semiconductor layer 4 between the source electrode 6 and the drain electrode 7.
FIG. 36 shows a thin film insulated gate FET having a gate electrode 2 formed on a substrate 1. This insulated gate FET comprises a substrate 1, a gate electrode 2 formed on the substrate 1, a gate insulating layer 3 covering the gate electrode 2, a first semiconductor layer 4, i.e., a thin silicon film, formed over the gate insulating layer 3, spaced apart second semiconductor layers 5a and 5b, i.e., doped thin silicon films, formed over the first semiconductor layer 4, a source electrode 6 (metal film) formed over the spaced apart second semiconductor layer 5a, and a drain electrode 7 (metal film) formed over the spaced apart second semiconductor layer 5b. A gap between the source electrode 6 and the drain electrode 7 is formed opposite to the gate electrode 2 and a portion of the first semiconductor layer 4 corresponding to the gap is a channel 8.
FIG. 37 shows a thin film insulated gate FET having electrodes, an insulator and semiconductor layers similar to those of the insulated gate FET of FIG. 38, except that the electrodes and semiconductor layers are formed in the reverse order on a substrate. That is, this thin film insulated gate FET comprises a substrate 1, a conductive source electrode 6 formed on the substrate 1, a conductive drain electrode 7 formed on the substrate 1, spaced apart second semiconductor layers [doped semiconductor layers) 5a and 5b formed respectively on the source electrode 6 and the drain electrode 7, a first semiconductor layer 4 formed on the spaced apart second semiconductor layers 5a and 5b and on the substrate 1, an insulating layer 3 formed on the first semiconductor layer 4, and a conductive gate electrode 2 formed on the insulating layer 3. A portion of the first spaced apart layer 4 corresponding to a gap between the spaced apart second semiconductor layers 5a and 5b is a channel 8.
The gate threshold voltage V.sub.th of such a thin film FET is dependent on the work function of the conductive material forming the gate electrode 2, the charge density and thickness of the gate insulating layer 3, and the effective charged state density N.sub.E and thickness of the first semiconductor layer 4.
In constructing an electronic circuit on a substrate by forming thin semiconductor films over the substrate by a plasma CVD process or a molecular beam epitaxy process, transistors respectively having similar film constructions are formed simultaneously on the substrate under the same film forming conditions deciding the foregoing parameters. Accordingly, the transistors have nearly the same gate threshold voltage V.sub.th.
In most cases, it is required to set a predetermined gate threshold voltage V.sub.th accurately for such a thin film FET in accordance with the purpose of the associated electronic circuit. On the other hand, since changing the material constituting the films and the film forming process or film forming conditions are the only means of adjusting the gate threshold voltage V.sub.th, the foregoing manufacturing conditions must be changed to construct FETs respectively having different gate threshold voltages. However, from the viewpoint of process management, it is undesirable to change the manufacturing conditions and, in view of productivity, it is desirable to keep the manufacturing conditions for the FETs with different V.sub.th 's as similar as possible. Furthermore, even if the manufacturing conditions could be changed, practically it is quite hard to control optionally the work function of the conductive material for forming the gate electrode 2, the charge density of the gate insulating layer 3 and the effective charged state density N.sub.E of the first semiconductor layer 4 in which the channel 8 is formed. Thus, the accurate regulation of the gate threshold voltage V.sub.th has been very difficult.
In some cases, it is required to form a plurality of thin film FETs respectively having different gate threshold voltages on a single substrate. However, it is impossible to meet such a requirement, when the thin film FETs are formed on the same substrate by using the same materials and under the same film forming conditions.